Feex·Hardware
Corrections

CPU corrections

519 CPU values were replaced or removed by the audit across 398 records, listed below with old value, new value, rule and evidence. 175 values that were empty are filled; browse them by rule.

All corrections · CPU · GPU

Browse by rule: L2 cache was stored per core (274) Cleanup pcie int to decimal (130) Benchmark row re-read from the exact PassMark page (108) Cleanup fx hyphen space (70) Two independent sources agree (30) Cleanup hedt no igpu (24) Cleanup pcie multi to max (19) Base clock was the configurable-TDP-down figure (18) Vendor specification applied (9) Codename or architecture from two sources (5) Cleanup pcie gen prefix (4) Codename from the vendor (2) Cleanup pcie scraped page null (1)

519 values · page 6 of 11 · replaced and removed values only

RecordFieldChangeRuleEvidence
Intel® Atom™ C2538 PCIe revision
Replaced
2 → 2.0 Cleanup pcie int to decimal
normalize to the dominant "N.0" format
Intel® Atom™ C2550 PCIe revision
Replaced
2 → 2.0 Cleanup pcie int to decimal
normalize to the dominant "N.0" format
Intel® Atom™ C2558 PCIe revision
Replaced
2 → 2.0 Cleanup pcie int to decimal
normalize to the dominant "N.0" format
Intel® Atom™ C2750 PCIe revision
Replaced
2 → 2.0 Cleanup pcie int to decimal
normalize to the dominant "N.0" format
Intel® Atom™ C2758 PCIe revision
Replaced
2 → 2.0 Cleanup pcie int to decimal
normalize to the dominant "N.0" format
Intel® Atom™ C3338 PCIe revision
Replaced
3 → 3.0 Cleanup pcie int to decimal
normalize to the dominant "N.0" format
Intel® Atom™ C3508 PCIe revision
Replaced
3 → 3.0 Cleanup pcie int to decimal
normalize to the dominant "N.0" format
Intel® Atom™ C3538 PCIe revision
Replaced
3 → 3.0 Cleanup pcie int to decimal
normalize to the dominant "N.0" format
Intel® Atom™ C3558 PCIe revision
Replaced
3 → 3.0 Cleanup pcie int to decimal
normalize to the dominant "N.0" format
Intel® Atom™ C3708 PCIe revision
Replaced
3 → 3.0 Cleanup pcie int to decimal
normalize to the dominant "N.0" format
Intel® Atom™ C3758 PCIe revision
Replaced
3 → 3.0 Cleanup pcie int to decimal
normalize to the dominant "N.0" format
Intel® Atom™ C3758R PCIe revision
Replaced
3 → 3.0 Cleanup pcie int to decimal
normalize to the dominant "N.0" format
Intel® Atom™ C3808 PCIe revision
Replaced
3 → 3.0 Cleanup pcie int to decimal
normalize to the dominant "N.0" format
Intel® Atom™ C3858 PCIe revision
Replaced
3 → 3.0 Cleanup pcie int to decimal
normalize to the dominant "N.0" format
Intel® Atom™ C3958 PCIe revision
Replaced
3 → 3.0 Cleanup pcie int to decimal
normalize to the dominant "N.0" format
Intel® Core™ 3 100U L2 cache (total)
Replaced
1,280 KB → 4,608 KB L2 cache was stored per core
Intel® Core™ 5 120U L2 cache (total)
Replaced
1,280 KB → 6,656 KB L2 cache was stored per core
Intel® Core™ 5 220U L2 cache (total)
Replaced
1,280 KB → 6,656 KB L2 cache was stored per core
Intel® Core™ 7 150U L2 cache (total)
Replaced
1,280 KB → 6,656 KB L2 cache was stored per core
Intel® Core™ i3-1005G1 L2 cache (total)
Replaced
512 KB → 1,024 KB L2 cache was stored per core
Intel® Core™ i3-10100 L2 cache (total)
Replaced
256 KB → 1,024 KB L2 cache was stored per core
Intel® Core™ i3-10100F L2 cache (total)
Replaced
256 KB → 1,024 KB L2 cache was stored per core
Intel® Core™ i3-10105F L2 cache (total)
Replaced
256 KB → 1,024 KB L2 cache was stored per core
Intel® Core™ i3-10110U L2 cache (total)
Replaced
256 KB → 512 KB L2 cache was stored per core
Intel® Core™ i3-1115G4 L2 cache (total)
Replaced
1,280 KB → 2,560 KB L2 cache was stored per core
Intel® Core™ i3-1115G4 Base clock
Replaced
1,700 MHz → 3,000 MHz Base clock was the configurable-TDP-down figure
stored 1700 MHz is the cTDP-down end of the Wikipedia base range 1700-3000 MHz; PassMark base 3000 MHz = the nominal (high-TDP) base
Intel® Core™ i3-1125G4 L2 cache (total)
Replaced
1,280 KB → 5,120 KB L2 cache was stored per core
Intel® Core™ i3-1125G4 Base clock
Replaced
900 MHz → 2,000 MHz Base clock was the configurable-TDP-down figure
stored 900 MHz is the cTDP-down end of the Wikipedia base range 900-2000 MHz; PassMark base 2000 MHz = the nominal (high-TDP) base
Intel® Core™ i3-1215U L2 cache (total)
Replaced
1,280 KB → 4,608 KB L2 cache was stored per core
Intel® Core™ i3-1220P L2 cache (total)
Replaced
1,280 KB → 6,656 KB L2 cache was stored per core
Intel® Core™ i3-1305U L2 cache (total)
Replaced
1,280 KB → 3,328 KB L2 cache was stored per core
Intel® Core™ i3-1315U L2 cache (total)
Replaced
1,280 KB → 4,608 KB L2 cache was stored per core
Intel® Core™ i3-4000M PCIe revision
Replaced
2 → 2.0 Cleanup pcie int to decimal
normalize to the dominant "N.0" format
Intel® Core™ i3-4110M PCIe revision
Replaced
2 → 2.0 Cleanup pcie int to decimal
normalize to the dominant "N.0" format
Intel® Core™ i3-8100 L2 cache (total)
Replaced
256 KB → 1,024 KB L2 cache was stored per core
Intel® Core™ i3-9100F L2 cache (total)
Replaced
256 KB → 1,024 KB L2 cache was stored per core
Intel® Core™ i3-N300 L2 cache (total)
Replaced
2,048 KB → 4,096 KB L2 cache was stored per core
Intel® Core™ i3-N305 L2 cache (total)
Replaced
2,048 KB → 4,096 KB L2 cache was stored per core
Intel® Core™ i5-10210U L2 cache (total)
Replaced
256 KB → 1,024 KB L2 cache was stored per core
Intel® Core™ i5-10300H L2 cache (total)
Replaced
256 KB → 1,024 KB L2 cache was stored per core
Intel® Core™ i5-10400 L2 cache (total)
Replaced
256 KB → 1,536 KB L2 cache was stored per core
Intel® Core™ i5-10400F L2 cache (total)
Replaced
256 KB → 1,536 KB L2 cache was stored per core
Intel® Core™ i5-10500 L2 cache (total)
Replaced
256 KB → 1,536 KB L2 cache was stored per core
Intel® Core™ i5-10500T L2 cache (total)
Replaced
256 KB → 1,536 KB L2 cache was stored per core
Intel® Core™ i5-10600K L2 cache (total)
Replaced
256 KB → 1,536 KB L2 cache was stored per core
Intel® Core™ i5-10600KF L2 cache (total)
Replaced
256 KB → 1,536 KB L2 cache was stored per core
Intel® Core™ i5-11260H L2 cache (total)
Replaced
1,280 KB → 7,680 KB L2 cache was stored per core
Intel® Core™ i5-11260H Base clock
Replaced
2,100 MHz → 2,600 MHz Base clock was the configurable-TDP-down figure
stored 2100 MHz is the cTDP-down end of the Wikipedia base range 2100-2600 MHz; PassMark base 2600 MHz = the nominal (high-TDP) base
Intel® Core™ i5-11300H L2 cache (total)
Replaced
1,280 KB → 5,120 KB L2 cache was stored per core
Intel® Core™ i5-11300H Base clock
Replaced
2,600 MHz → 3,100 MHz Base clock was the configurable-TDP-down figure
stored 2600 MHz is the cTDP-down end of the Wikipedia base range 2600-3100 MHz; PassMark base 3100 MHz = the nominal (high-TDP) base